HRBUZZ Staffing Solutions Pvt. Ltd.

Experience: 8-12 Years

Location: Ahmedabad

Education: BE/ME

Description:

Should have good knowledge about all DFT concepts.

Scan insertion and validation, BIST insertion and validation, ATPG and Pattern Validation w/wo Timing, DFT mode timing Analysis and sign off.

Work experience on various DFT architectures. Knowledge of protocol like IEEE1149.1, IEEE1149.6, IEEE1687 and IEEE1500.

Worked on Pattern diagnosis and Familiarity with ATE, silicon bring up. Should have done 4 tape outs.

Technical Skills:

- Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level

- Synopsys tools: DFT MAX, TetraMAX

- Cadence tools: RTL Compiler, Encounter Test

- Mentor Graphics tools: Tessent tool chain, TestKompress

- Debussy, VCS/Questa/IUS

- PT tool from Synopsys

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